CSCI E-92: Application Note 25

Forcing Precise BusFaults using the Auxiliary Control Register - ACTLR
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In order to force BusFault core interrupts to be associated more
precisely with the specific address where the BusFault may have
occurred, the K70's write buffer can be disabled.  Because this causes
processor performance to be diminished, this modification should be
implemented only when determining the exact address at which a
BusFault has occurred.  Remember to delete the instructions that
disable the write buffer once the BusFault error has been corrected.

The write buffer is disabled by setting the DISDEFWBUF bit (bit 1) in
the ACTLR (Auxiliary Control Register) to 1.  This is accomplished as
follows:

SCB_ACTLR = SCB_ACTLR_DISDEFWBUF_MASK;

Reenabling the write buffer is accomplished as follows:

SCB_ACTLR = 0;


The information below describes the Auxiliary Control Register in detail
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See the Cortex-M4 Revision r0p1 Technical Reference Manual
DDI0439C_cortex_m4_r0p1_trm section 4.3.1 on pages 4-11 to 4-12.


The Auxiliary Control Register provides bits to disable functions of
the processor.  These are: (1) IT folding, (2) write buffer use for
accesses to the default memory map, and (3) interruption of
multi-cycle instructions.


Here is the specific information.

Bits 31-10 and 7-3 are reserved.

DISOOFP, bit 9, Disables floating point instructions completing out of
  order with respect to integer instructions.  This is implemented only
  in a Cortex-M4F device.

DISFPCA, bit 8, Disables automatic update of CONTROL.FPCA.  This is
  implemented only in a Cortex-M4F device.

DISFOLD, bit 2, When set to 1, disables IT folding.  See About IT
  folding below for more information.

DISDEFWBUF, bit 1, When set to 1, disables write buffer use during
  default memory map accesses. This causes all BusFaults to be precise
  BusFaults but decreases performance because any store to memory must
  complete before the processor can execute the next instruction.

		Note

  This bit only affects write buffers implemented in the Cortex-M4
  processor

DISMCYCINT, bit 0, When set to 1, disables interruption of load
  multiple and store multiple instructions. This increases the interrupt
  latency of the processor because any LDM or STM must complete before
  the processor can stack the current state and enter the interrupt
  handler


About IT folding

In some situations, the processor can start executing the first
instruction in an IT block while it is still executing the IT
instruction.  This behavior is called IT folding, and improves
performance, however, IT folding can cause jitter in looping.  If a
task must avoid jitter, set the DISFOLD bit to 1 to disable IT folding
before executing the task.